Requirements

Expected technologies

Verilog

SystemVerilog

SoC

ARM CSS

DDR4/DDR5

PCIe Gen5

Gen4 IP

Optional technologies

Design Compiler

SpyGlass CDC/DFT

Fusion Compiler

Python

TCL

Linux

firmware

Operating system

Linux

Our requirements

• Min. 5 years of experience in a similar position
• Strong RTL design experience using Verilog/SystemVerilog, with proven SoC block integration
• Practical experience with ARM CSS, DDR4/DDR5 memory controller and PHY design, PCIe Gen5 or Gen4 IP
• Deep understanding of AMBA protocols (AXI, ACE, AHB, APB) and SoC interconnect architectures
• Experience with low-power design techniques and clock/reset domain crossing issues
• Fluency in English
• Creative problem-solving abilities and decision-making skills
• Fluent Polish required
• Residing in Poland required

Optional

• Hands-on experience with Synopsys tooling (Design Compiler, SpyGlass CDC/DFT, Fusion Compiler)
• Exposure to formal verification techniques, CDC/RDC analysis, and DFT methodologies
• Scripting skills (Python, TCL) for automation and RTL flow enhancement
• Knowledge of high-speed SerDes design and signal integrity considerations
• Understanding of hardware/software co-design, Linux device drivers, or firmware development

Your responsibilities

• Design and implement RTL for complex, multi-core SoC components, including high-speed memory controllers (DDR5/6), PCIe Gen5 interfaces, and coherent interconnect fabrics (AXI/ACE)
• Integrate industry-standard and custom IP blocks such as ARM Cortex subsystems, DDR PHY/CTRL, PCIe, and NoC/AXI interconnects
• Collaborate closely with verification, synthesis, backend, and architecture teams on microarchitecture and performance optimization
• Address challenges in clock/reset domain crossing, power management, and low-latency data paths
• Participate in design reviews, static timing analysis (STA), and signal integrity debug cycles