Requirements

Expected technologies

SystemVerilog

UVM

SoC

ARM CSS

DDR4/DDR5

PCIe Gen5

Gen4 IP

Optional technologies

Synopsys VCS

SpyGlass

Verdi

JasperGold

Python

TCL

Perl

Ethernet

DPDK

Our requirements

• Min. 5 years of experience in a similar position
• Strong experience in RTL verification using SystemVerilog and UVM methodology
• Familiarity with SoC design elements such as ARM CSS, DDR5/DDR6, PCIe Gen4/Gen5
• Solid understanding of clock/reset domain crossing issues, assertion-based verification, and coverage analysis
• Proficiency in debugging complex SoC designs using waveform and static analysis tools
• Fluency in English
• Creative problem-solving abilities and decision-making skills
• Fluent Polish required
• Residing in Poland required

Optional

• Experience with Synopsys VCS, SpyGlass, Verdi, JasperGold or other formal verification tools
• Knowledge of DFT insertion, low-power verification, and hardware/software co-verification
• Scripting proficiency (Python, TCL, Perl) for automation and environment enhancement
• Exposure to networking protocols and packet processing (Ethernet, DPDK)
• Familiarity with CI/CD pipelines for verification workflows

Your responsibilities

• Develop scalable SystemVerilog UVM testbenches for complex SoC IP including multi-core processors, DDR5 memory interfaces, PCIe Gen5, and high-speed interconnects
• Write constrained-random, directed, and coverage-driven tests, ensuring functional and performance closure
• Analyse and debug complex SoC issues, including clock/reset domain crossings, using tools like SimVision, Verdi, or SpyGlass CDC
• Collaborate with design, integration, DFT, and architecture teams to improve test coverage, verification quality, and debug efficiency
• Integrate formal verification assertions and CDC/RDC checks into the verification flow