About the project

• We’re building a next-generation high-performance SoC platform targeting cloud and AI workloads. Join us as a Digital Design Engineer to design cutting-edge digital blocks, including multi-core ARM Cortex subsystems (ARM CSS), DDR5 memory controllers, PCIe Gen5 interfaces, and advanced SoC interconnects.
• By joining us, you become a member of the Embedded Competence Center at Sii - an internal organizational unit bringing together more than 500 specialists across Poland! We are currently working on approximately 100 projects for 50 clients across various industries, including automotive, IoT, telecommunications, and medical. We focus on development and knowledge exchange by organizing Embedded Academies, training, technical mentoring or enabling project changes.

Your responsibilities

• Design and implement RTL for complex, multi-core SoC components, including high-speed memory controllers (DDR5/6), PCIe Gen5 interfaces, and coherent interconnect fabrics (AXI/ACE)
• Integrate industry-standard and custom IP blocks such as ARM Cortex subsystems, DDR PHY/CTRL, PCIe, and NoC/AXI interconnects
• Collaborate closely with verification, synthesis, backend, and architecture teams on microarchitecture and performance optimization
• Address challenges in clock/reset domain crossing, power management, and low-latency data paths
• Participate in design reviews, static timing analysis (STA), and signal integrity debug cycles

Our requirements

• Min. 5 years of experience in a similar position
• Strong RTL design experience using Verilog/SystemVerilog, with proven SoC block integration
• Practical experience with ARM CSS, DDR4/DDR5 memory controller and PHY design, PCIe Gen5 or Gen4 IP
• Deep understanding of AMBA protocols (AXI, ACE, AHB, APB) and SoC interconnect architectures
• Experience with low-power design techniques and clock/reset domain crossing issues
• Fluency in English
• Creative problem-solving abilities and decision-making skills
• Fluent Polish required
• Residing in Poland required

Optional

• Hands-on experience with Synopsys tooling (Design Compiler, SpyGlass CDC/DFT, Fusion Compiler)
• Exposure to formal verification techniques, CDC/RDC analysis, and DFT methodologies
• Scripting skills (Python, TCL) for automation and RTL flow enhancement
• Knowledge of high-speed SerDes design and signal integrity considerations
• Understanding of hardware/software co-design, Linux device drivers, or firmware development

Technologies we use

What we offer

• Great Place to Work since 2015 - it’s thanks to feedback from our workers that we get this special title and constantly implement new ideas

• Employment stability - revenue of PLN 2.1BN, no debts, since 2006 on the market

• We share the profit with Workers - over PLN 60M has already been allocated for this aim since 2022

• Attractive benefits package - private healthcare, benefits cafeteria platform, car discounts and more

• Comfortable workplace – class A offices or remote work

• Dozens of fascinating projects for prestigious brands from all over the world – you can change them thanks to Job Changer application

• PLN 1 000 000 per year for your ideas - with this amount, we support the passions and voluntary actions of our workers

• Investment in your growth – meetups, webinars, training platform and technology blog – you choose

• Fantastic atmosphere created by all Sii Power People